主讲人：陈耿杰博士
报告时间：2019年9月4号，9:30-11:00
报告地点：数计学院4号楼229
报告题目1：VLSI Routing: Seeing Nano Tree in Giga Forest
报告摘要：We are using nanometer-sized transistors and gigahertz clock frequency in very large scale integration (VLSI). Under such extreme conditions, timing, power, manufacturability and reliability are all crucial issues in VLSI design. The tree structure is the major topology used in VLSI routing. Optimizing the tree and the forest is essential for a successful design flow. However, the problems are in general challenging. First, even for many single-net routing problems, finding an optimal tree from a huge candidate forest is already NP-hard. Second, for multiple-net routing, a large number of trees need to be built on the chip by sharing resources and need to be well coordinated for avoiding conflicts. Third, in order to achieve a full-flow success, it is also necessary to foresee routing trees and to consider routability in early stages (e.g., placement). This talk will introduce the efficient and effective algorithms that we devised for tackling the three levels of challenges with not only practical considerations in VLSI design but also mathematical rigorousness and guarantee.
个人简介：Gengjie Chen is currently a Principle Software Engineer with Giga Design Automation, Shenzhen. He received the Ph.D. degree from the Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, in 2019, and received the B.Sc. degree from the Department of Electronic and Communication Engineering, Sun Yat-sen University, Guangzhou, China, in 2015. His research interests include combinatorial optimization, numerical optimization and electronic design automation. He published 14 papers in TCAD, DAC, ICCAD, DATE and ASPDAC during his Ph.D. study. He also received the first place at ACM Student Research Competition in 2019, the first place at ACM SIGDA Student Research Competition in 2018, the best paper award at ICCAD 2017, the Hong Kong Ph.D. Fellowship from 2015 to 2019, and seven ICCAD/ISPD contest awards including four championships. He has interned in Cadence, Austin, TX, in 2017, and Synopsys, Mountain View, CA, in 2016.
