学术报告一：Modern Circuit Placement
时间: 9月6日上午, 9:00-11:30
地点: 数计学院2号楼309室
演讲人: Yao-Wen Chang Associate Dean & MXIC Chair Professor / Distinguished Professor College of EECS, National Taiwan University, Taipei,Taiwan
Abstract:
A modern chip often contains large numbers of pre-designed macros (e.g., embedded memories, IP/analog blocks) and standard cells of very different sizes. The fast-growing design complexity with large-scale mixed-size macros and standard cells has incurred significant challenges to modern circuit placement. In this talk, we first survey published techniques for modern circuit placement and then present our recent techniques for standard cell, large macro, datapath, and FPGA placement. We also discuss the strengths and weaknesses of existing techniques for modern circuit placement. Finally, we provide some future research directions for modern circuit placement.
学术报告二：Design for Manufacturability for Sub-14nm Technologies
时间: 9月6日下午, 14:00-16:00
地点: 数计学院2号楼309室
演讲人: Yao-Wen Chang Associate Dean & MXIC Chair Professor / Distinguished Professor College of EECS, National Taiwan University, Taipei,Taiwan
Abstract:
As process nodes continue to shrink, the semiconductor industry faces severe manufacturing challenges. Four most expected technologies may push the limits of lithography: multiple patterning lithography, extreme ultraviolet lithography, electron beam lithography, and directed self-assembly. We investigate the most critical design challenges of the four technologies and provide our solutions, which can contribute to the continuing scaling of the CMOS technology. Finally, we provide some future research directions for the addressed technologies.
Biography:
Yao-Wen Chang received the B.S. degree from National Taiwan University (NTU) in 1988, and the M.S. and Ph.D. degrees from the University of Texas at Austin in 1993 and 1996, respectively, all in computer science. He is currently the MXIC Chair Professor of the Dept. of Electrical Engineering and Associate Dean of the EECS College, National Taiwan University. He was a visiting scholar at MIT, USA in 2014 and a visiting professor at Waseda University, Japan 2004—2011.
His current research interests lie in electronic design automation (EDA) and manufacturability. He has coauthored one textbook on electronic design automation (EDA) and one book on routing and over 250 ACM/IEEE conference/journal papers, including highly cited papers on floorplanning, placement, routing, and FPGA switch module design. Dr. Chang has received many research/teaching awards, including four awards at the 50th ACM/IEEE Design Automation Conference (DAC) in 2013 (e.g., the 1st Most Papers in the Fifth Decade 2004-2013 [#1 worldwide with 34 papers] and now 50-Club of DAC [top-5 author of all times]), the sole six 1st-place awards of recent ACM/IEEE EDA contests on circuit placement, clock network synthesis, gate sizing, and timing analysis, seven best paper awards and 22 best paper nominations, the Distinguished Research Award from the Ministry of Science and Technology of Taiwan (highest honor; 3 times), the IBM Faculty Awards (three times), and the distinguished teaching award from NTU (highest honor). He was ranked #1 worldwide among 40K+ researchers by the Microsoft Academic Search Database for Recent Five-Year Citations in the Hardware and Architecture Domain during November 2011 -- March 2012.
Dr. Chang is currently the Vice President of Technical Activities of the IEEE Council on EDA (CEDA) and the past chair of IEEE/ACM ICCAD. He has served on the editorial boards of IEEE TCAD, IEEE TVLSI, IEEE D&T, etc. and on the program committees of all important EDA conferences, and as program / general / steering committee chairs of ISPD and program chairs of ASP-DAC, ICCAD, and FPT. He has also served as an independent board director of Genesys Logic, a technical consultant of Faraday, MediaTek, and RealTek, and the Chair of the EDA Consortium of Taiwan Ministry of Education. Dr. Chang is a co-founder of Maxeda Technology. He is an IEEE Fellow.
