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发表日期:2018年10月26日      

上海科技大学周平强教授学术报告

 

报告题目:Enabling the Design of Energy-Efficient and Reliable Processor Chips

报告人:周平强,教授,上海科技大学

报告时间:2018年10月29号,10:00am-12:00am

报告地点:数计学院4号楼第二报告厅

 

Abstract:Power has been a primary challenge in the design of current and future processor chips. Reducing supply voltage VDD is a popular way to meet power budgets, which can be achieved by either decreasing nominal supply voltage VDD aggressively with technology scaling, or by applying runtime power saving techniques such as dynamic voltage scaling (DVS). In this talk, I will present two related topics: 1) energy-efficient processor chip design using DVS technique, enabled by integrated voltage regulators and 2) reliable chip power supply with the aid of emergency detection system. In particular, I will present a few examples to show how machine learning techniques can be used to build such an emergency detection system.

Speaker Bio: Pingqiang Zhou received the M.E. degree from Tsinghua University, Beijing, China and a Ph.D. degree from the University of Minnesota. He has been a professor with the School of Information Science and Technology at ShanghaiTech University, Shanghai, China. He was with the University of California, Berkeley as a visiting scholar in 2015.
Dr Zhou’s research interests include computer architecture, VLSI design automation, intelligent chip design and hardware security. He is serving on the technical program committee/as session chairs of top conferences such as DAC, ICCAD and ASP-DAC, and is also the invited reviewer for many top journals and conferences in the areas of VLSI design automation, computer architecture and VLSI design.



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