Talk 1: Layout Decomposition for Triple Patterning Lithography
To extend the 193nm immersion lithography for 20nm technology node and beyond, various multiple patterning lithography techniques have been developed to achieve finer pitches. Although litho-etch-litho-etch(LELE) based double patterning lithography (DPL) has become a key enablement for 20 nm and 16/14 nm nodes, it might not overcome the lithography bottleneck as the process continues to scale down to the 10nm or 7nm regime. On the other hand, LELELE based triple patterning lithography (TPL) is a natural extension of DPL and is more flexiblein mask arrangement than DPL.
The focus of this talk is on a TPL layout decomposition problem for cell-based designs, which asks to minimize a weighted sum of coloring conflictsand stitches for the metal 1 layer that is observed to be one of the most hard-to-decompose layers. It will show how to extend a prior graph-basedapproach to solve the problem optimally under certain assumptions. Furthermore, several methods to substantiallyreduce the graph size and hence to accelerate the extendedapproach will be explained as well. Finally, experimental results to support the robustness of this TPL layout decomposer will be presented and discussed.
Talk 2: On Refining Cell-based Detailed Placement for Triple Patterning Lithography
The focus of this talk is on a cell-based detailed placementrefinement problem for triple patterning lithography (TPL), whichasks to find a refined detailed placement solution as wellas a valid TPL layout decomposition under the objective ofminimizing the number of stitches for the metal 1 layer and the overall half-perimeter wirelength. The techniques of white space insertion, cell flipping, adjacent-cell swapping, and vertical cell movement, are considered in the problem to optimize the solution quality.
First, (resource-constrained) shortest-path-based algorithms will be presented for several TPL-aware single-row placement problemsthat allow or disallow perturbing a given cell ordering. Next, an approach based on the single-row algorithmswill be introduced for the TPL-aware detailed placement refinement problem. Finally, extensive experimentalresults will be shown to demonstrate the effectiveness and efficiency of all aforementioned algorithms.
Ting-Chi Wang received the B.S. degree in Computer Science and Information Engineering from National Taiwan University, Taipei, Taiwan, and the M.S. and Ph.D. degrees in Computer Sciences from the University of Texas at Austin, USA. He is currently a Professor in the Department of Computer Science and the Director of Institute of information Systems and Applications, National TsingHua University, Hsinchu, Taiwan. His major research interest is in VLSI physical design automation.
Dr. Wang received Best Paper Awards respectively from 2006 ASP-DAC and 2015 ISPD for his works on redundant via insertion and triple patterning layout decomposition. He supervised a team to win the first place at 2008 ISPD Global Routing Contest. He was the General Chair of 2015 SASIMI and served on the technical program committees of major EDA conferences, including ASP-DAC, DAC, DATE, ICCAD, and ISPD. He is currently an Associate Editor of ACM TODAES.